The present invention relates to a semiconductor device, and more particularly, to an architecture of a highly integrated semiconductor memory device including a plurality of memory banks for storing data and a variety of internal circuits for performing input/output operations.
A semiconductor memory device such as a double data rate synchronous DRAM (DDR SDRAM) stores or outputs data according to a command received from a data processor device, e.g., a central processor unit (CPU). When a read command is inputted from the CPU, data is stored in a memory cell of the semiconductor memory device, corresponding to an address received from the CPU. When a write command is inputted from the CPU, data is output from a memory cell corresponding to an address received from the CPU.
A semiconductor memory device includes tens of millions or more memory cells. A set of memory cells is referred to as a memory bank. The number of memory banks in the semiconductor memory device is different according to the design, and continues to increase as the semiconductor memory device is developed to achieve a large capacity.
FIG. 1 is a circuit diagram illustrating read and write operations of a conventional semiconductor memory device. For convenience of explanation, only one memory cell having the reference numeral of 110 is shown in FIG. 1.
The read operation of the conventional semiconductor memory device will be described briefly with reference to FIG. 1.
As a read command is inputted to the semiconductor memory device, an inputted row address is decoded to enable a corresponding word line WL. Then, a cell transistor T1 of the memory cell 110 is turned on so that charge sharing occurs between a cell capacitor C1 and a bit line BL or a bit line bar /BL. As a result, there is a slight voltage difference between the bit line BL and the bit line bar /BL.
A bit line sense amplifier 120 senses and amplifies the voltage difference. That is, when the potential of the bit line BL is higher than that of the bit line bar /BL, the voltage of the bit line BL is amplified to a pull-up power supply voltage RTO and that of the bit line bar /BL is amplified to a pull-down power supply voltage SB. On the contrary, when the potential of the bit line BL is lower than that of the bit line bar /BL, the voltage level of the bit line BL is amplified to the pull-down power supply voltage SB and that of the bit line bar /BL is amplified to the pull-up power supply voltage RTO.
An inputted column address is also decoded to activate a column selection signal YI. Then, a column selector 130 is enabled so that the bit line BL and bit line bar /BL are connected to the segment input/output line SIO and the segment input/output line bar /SIO, respectively. That is, the data on the bit line BL is transferred to the segment input/output line SIO and the data on the bit line bar /BL is transferred to the segment input/output line bar /SIO.
Thereafter, an input/output switch 140 is enabled in response to an input/output control signal CTR_IO so that the segment input/output line SIO and the segment input/output line bar /SIO are connected to the local input/output line LIO and the local input/output line bar /LIO. That is, the signal on the segment input/output line SIO is transferred to the local input/output line LIO, and the signal on the segment input/output line bar /SIO is transferred to the local input/output line bar /LIO. A read driver 150 receives the data from the local input/output line LIO and the local input/output line bar /LIO to drive a global input/output line GIO.
Resultantly, the data in the memory cell 110 is transferred from the bit line BL and the bit line bar /BL to the segment input/output line SIO and the segment input/output line bar /SIO, respectively, in response to the column selection signal YI. The data on the segment input/output line SIO and the segment input/output line bar /SIO is transferred to the local input/output line LIO and the local input/output line bar /LIO, respectively, in response to the input/output control signal CTR_IO. The data on the local input/output line LIO and the local input/output line bar /LIO is transferred to the global input/output line GIO by the read driver 150. Finally, the data on the global input/output line GIO is outputted to the outside through a corresponding input/output pad (not shown).
In a write operation, the data received from the outside is transferred in the reverse direction, compared with the read operation. That is, the data inputted through the input/output pad is transferred through the global input/output line GIO, and transferred to the local input/output line LIO and the local input/output line bar /LIO by a write driver 160. Then, the data is transferred to the segment input/output line SIO and the segment input/output line bar /SIO, transferred to the bit line BL and the bit line bar /BL, and finally stored in the memory cell 110.
FIG. 2 is a block diagram illustrating a memory bank structure of a conventional semiconductor memory device. For convenience of explanation, a semiconductor memory device having eight memory banks will be described as an example.
Referring to FIG. 2, the semiconductor memory device includes first to eighth memory banks, and row control circuit regions and column control circuit regions corresponding to the respective memory banks. The first memory bank 210, the first row control circuit region 230 and the first column control circuit region 250 corresponding to the first memory bank 210 will be described, as an example.
As described above, the first memory bank 210 includes a plurality of memory cells. The first row control circuit region 230 includes circuits for controlling row access to the first memory bank 210, and the first column control circuit region 250 includes circuits for controlling column access to the first memory bank 210.
Although not shown specifically, the first row control circuit region 230 includes a row decoder, a power supply voltage controller and a row redundancy controller. The row decoder decodes an address received from the CPU to select the word line WL (see FIG. 1). The power supply voltage controller controls the pull-up power supply voltage RTO and the pull-down power supply voltage SB applied to the bit line sense amplifier 120. Here, the pull-up power supply voltage RTO and the pull-down power supply voltage SB are voltages generated based on the external power supply voltage and the ground voltage. The row redundancy controller replaces a word line connected to a defective memory cell by another word line connected to a normal memory cell.
Although not shown specifically, the first column control circuit region 250 includes a column decoder, a read driver, a write driver and a column redundancy controller. The column decoder decodes an address received from the CPU to select column selection signal YI (see FIG. 1) for the corresponding memory cell. The read driver 150 (see FIG. 1) outputs data read from the memory bank according to the read command. The write driver 160 (see FIG. 1) transfers the data received from the outside to the corresponding memory bank according to the write command. The column redundancy controller replaces a column selection signal YI corresponding to a defective memory cell to another column selection signal YI corresponding to a normal memory cell. Here, the column redundancy operation is performed by replacing a column address corresponding to the defective memory cell to a column address corresponding to the normal memory cell.
The first, second, fifth and sixth memory banks are disposed in a line along a row direction. The third, fourth, seventh and eighth memory banks are also disposed in a line along the row direction. Between the set of the first, second, fifth and sixth memory banks and the set of the third, fourth, seventh and eighth memory banks, a peripheral circuit region 270 is disposed.
The peripheral circuit region 270 includes a plurality of pads (not shown) for receiving a power supply voltage, a data, an address, an external command, a clock signal and the like, and a plurality of transfer lines for transferring the signals inputted through the pads. The semiconductor memory device performs a variety of operations based on the signals inputted through the pads.
The row control circuit regions and the column control circuit regions also include a plurality of transfer lines, respectively. The transfer lines include power supply voltage lines, address lines and test lines. Circuits included in the row control circuit regions and the column control circuit regions receive power supply voltages through the power supply voltage lines, addresses through the address lines, and signals related to a variety of test operations through the test lines. That is, each of the first to eighth row control circuit regions includes a power supply voltage line, an address line and a test line, and each of the first to eighth column control circuit regions also includes a power supply voltage line, an address line and a test line.
As a semiconductor memory device becomes highly integrated, the efforts to reduce the chip size of the semiconductor memory device are being continued to improve the productivity. Actually, as the chip size decreases, the number of chips per wafer increases, resulting in production cost economies. However, in the conventional memory bank structure of the semiconductor memory device, it is difficult to reduce the chip size because of power supply voltage lines, address lines and test lines for each row control circuit region and column control circuit region.
Recently, as the capacity of the semiconductor memory device increases, the number of memory banks and thus the required size of the row control circuit regions and the column control circuit regions also increase accordingly. Consequently, the increasing number of power supply voltage lines, address lines and test lines places a burden on the chip size.